2 BIT COUNTER 1 INPUT CODE

have a reset condition, but not a default. If N_button_signal = '1' and N_button_signal_del = '0' then - rising edgeĬounter <= counter + '1' - or somethingĤ) have a 2 bit signal (reg in Verilog I think) as a counter that you could output. the principle will hold true, the syntax will change in Verilog though. (you would do the opposite for a active high signal) in VHDL you'd have this.

if the original is '1' and the delayed is '0' then you've got a rising edge detect. then compare the original with the delayed. to do this delay your button signal by one clock cycle on your fast clock. (when your finger is down then the value is '0') then you do a rising edge detect. you need to do an edge detect on that signal to excite your binary output. so on start-up you'll see '00'.ģ) does not matter whether you make your button active high or low.

2 BIT COUNTER 1 INPUT CODE

I'm not that well versed in Verilog, I've mostly used VHDL but this might help you.ġ) yes you are quite right you will need some denouncing for your switch these are common and you can find some code for it online.Ģ) have a power on/reset condition for your binary output. Hello, Ill try to answer a question as I seem to only leech off the boards so forgive me if this isn't that helpful.

2 bit counter 1 input